1. Field of the Invention
This invention relates to a microprocessor design and more particularly to the generation of a zero bit status flag in a microprocessor.
2. Description of the Related Art
Conventional microprocessors can be used with internal and/or external memory for storing both instructions and data. One limiting factor in the performance of such a microprocessor is the memory access time. Memory access time is affected by several factors including how efficiently the microprocessor can write the address to the address bus and generate the necessary "READ" signals to activate the memory as well as the speed of the memory itself. Once the data is received by the microprocessor, several other steps may also be required which will add to the total memory access time. These steps include load alignment and zero bit updating described below.
Load alignment is often performed by microprocessors designed to receive data having any one of a variety of data formats. For example, data can vary in (i) the number of bits in the data word (i.e. 8, 16, 32, 64 bits etc.), (ii) the location of those bits within the data word (i.e. upper-most bits, lower-most bits, center bits, etc.), and (iii) the byte storage format (i.e. big-endian, little-endian, etc.). Such microprocessors have a load alignment circuit which converts the received data into a format compatible with the arithmetic logic unit (ALU) of the microprocessor. A load aligner sometimes reformats (aligns) the retrieved data word by first reordering the bits and by then sign extending the most significant bit leaving the reformatted word in a destination register. In such microprocessors, load alignment must be completed before the memory access may be considered complete.
A zero bit (z-bit) update sets the z-bit of a status register in the microprocessor. A z-bit update may be performed in microprocessors having a specialized instruction set which includes instructions whose execution depends on the value of a destination register. For example, a "branch on register value zero" or "move on register value zero" instruction will cause the microprocessor to branch, or move, respectively, if the z- bit in the destination register is zero.
Such branch and move instructions execute more efficiently in microprocessors having a status register associated with the destination register. In this case the status register contains a z-bit indicating whether the current value of the destination register is zero. The z-bit is updated according to a zero flag (z-flag) signal generated by performing a zero detect on the data most recently written to the destination register. Destination registers generally contain data either moved from the arithmetic logic unit (ALU) or data retrieved from memory. In either case, the z-bit of the status register must be updated prior to the execution of such an instruction which must test the value of the z-bit. Therefore, when data is loaded from memory to a destination register, the associated status register must also be updated before the memory access is considered complete.
Conventional microprocessors first load align data retrieved from memory and then update a status register responsive to the value of the retrieved data in a sequential fashion. The retrieved data is first aligned. Then a z-flag is generated from the aligned data. Therefore, the total memory access time of a conventional microprocessor is dependent on the time required to first load align the data and to then generate the z-flag and update the z-bit.
Decreased memory access times allow for a decreased instruction cycle of a microprocessor. Therefore, decreased memory access times are desirable to achieve increased microprocessor performance. Thus, there is a need for a microprocessor that load aligns data and updates the z-bit in a decreased memory access time.